A frequency synthesizer includes a Phase Locked Loop (PLL) circuit that divides a frequency signal output from a voltage control oscillator by a frequency divider, extracts a phase difference between a phase of the divided frequency signal and a phase of a reference frequency signal by a phase comparator, and feeds a control voltage corresponding to the phase difference back to the voltage control oscillator via a loop filter, and the frequency synthesizer uses the PLL circuit to output a stable frequency signal. Then, the frequency synthesizer variously varies the dividing number of the frequency divider and a dividing number of a frequency divider disposed on the reference frequency signal side so as to output the frequency signal of a desired frequency.
As a method for switching the frequency of the frequency signal output from the above-described frequency synthesizer at a high speed, there has been a method that increases the frequency of the reference frequency signal. However, using the reference frequency signal of the high frequency increases a step width of an output frequency switched corresponding to the dividing number of the frequency divider, thus failing to perform a fine frequency adjustment.
Therefore, as a method for ensuring the fine frequency adjustment while supplying the frequency synthesizer with the reference frequency signal of the high frequency, there has been a method that use a Direct Digital Synthesizer (DDS) as a signal source of the reference frequency signal. The DDS reads amplitude data from a waveform table based on phase data output corresponding to an input timing of a clock signal, thus obtaining the frequency signal of the desired frequency. Using the signal generated by the DDS as the reference frequency signal realizes the high speed switching of the frequency of the frequency signal output from the frequency synthesizer while finely varying.
However, the frequency signal output from the DDS includes a spurious component, and the spurious component causes a quality of the frequency signal output from the frequency synthesizer to decrease. While there are various causes to generate the spurious component, as one of them, there is a case where a higher harmonics component due to a frequency (clock frequency) of the clock signal that causes the DDS to operate appears as a folding noise (aliasing) within a used frequency band of the DDS.
Here, Patent Document 1 discloses a configuration where the frequency synthesizer using the DDS includes a program frequency divider between a reference oscillator that generates the clock signal and the DDS, and preliminarily calculates the frequencies of the spurious corresponding to an output frequency Fo of the DDS, so as to set a dividing of the program frequency divider such that the clock signal that does not have the frequencies of the spurious within a range of the predetermined frequency is supplied to the DDS.